The Tau Scaling Law, presented at ISCAS 2026 in Shanghai, reframes chip optimization around signal transit time rather than transistor size. The first LogicFolding chip reports 238 million transistors per square millimeter on older lithography. Every figure is self-reported.
For five decades, the semiconductor industry operated under a single organizing principle: fit more transistors into a smaller space, roughly doubling count every two years. But as process nodes have pushed below 5nm, the physical limits of miniaturization have collided with sharply rising costs. Advanced-node designs now routinely exceed $1 billion per project.
Huawei's new Tau Scaling Law, presented by He Tingbo at the 2026 IEEE International Symposium on Circuits and Systems in Shanghai, proposes a different optimization target: instead of minimizing the distance between transistors, engineers should minimize τ, the signal transit time across the entire computing stack. The relevant question becomes not how small you can make a transistor but how fast a signal can travel from one end of a system to the other, through every layer of hierarchy from circuit paths up to data center interconnects.
The shift matters practically because signal-latency optimization does not require the extreme ultraviolet lithography machines that Western foundries use to manufacture chips at the leading edge. Huawei has been blocked from acquiring those machines since 2019. The architecture built around the Tau principle, called LogicFolding, is explicitly designed to achieve density gains without depending on equipment China cannot access.
LogicFolding addresses the traditional flat 2D chip layout by folding circuits into a vertical 3D structure, stacking layers of logic directly on top of each other rather than side by side. The result is a significant reduction in internal wiring length for critical signal paths, reducing both latency and power consumption without requiring a newer manufacturing process. Huawei reports a 53.5% increase in transistor density, reaching 238 million transistors per square millimeter, up from 155 MTr/mm² on conventional designs at comparable process nodes, plus a 41% improvement in performance-core energy efficiency and a peak clock speed of 3.1 GHz.
The 238 MTr/mm² figure requires context. TSMC's current 3nm process achieves approximately 280 to 300 million transistors per square millimeter. Qualcomm's Snapdragon 8 Elite runs performance cores at a reported 5.0 GHz, nearly 2 GHz faster than Huawei's stated peak. Bloomberg and the Taipei Times separately confirmed that the manufacturing gap between TSMC and SMIC-plus-Huawei stands at approximately five years.
Huawei projects that chips built under the Tau framework will reach transistor density equivalent to a 1.4nm process by 2031. TSMC plans actual 1.4nm mass production beginning 2028. Whether density-equivalent chips built on older lithography deliver comparable performance, yield rates, and manufacturing reliability to an actual 1.4nm chip has not been established. Every performance figure in Huawei's announcement is self-reported, with no independent verification methodology publicly available. The Kirin 2026 chip, shipping to consumers in fall 2026, will provide the first real test.
